In recent years, with the further development of electronic products towards miniaturization and multifunctionality, chip sizes have become smaller and more diverse, with a significant increase in the number of output and input pins. This has made the development of 3D packaging, fan-shaped packaging (FOWLP/PLP), micro wire bonding technology, system packaging (SiP), chiplet, and other technologies one of the best choices to continue Moore's Law. The proportion of advanced packaging technology in the entire packaging market is gradually increasing, Expected to become the mainstream development direction. At present, the proportion of advanced packaging in China is significantly lower than that in the world. With the development of the domestic semiconductor industry, the proportion of advanced packaging is expected to accelerate.
01 | Industry Background: Semiconductor Packaging. Semiconductor packaging is the final step in the semiconductor manufacturing process, which refers to the process of processing a tested wafer into an independent chip. It involves placing the produced semiconductor device into a plastic, ceramic, or metal shell with support and protection, and connecting it to external drive circuits and other electronic components. The development process of semiconductor packaging has gone through a total of five stages of global integrated circuit packaging technology so far. It is generally believed that the first three stages belong to traditional packaging, while the fourth and fifth stages belong to advanced packaging. The current mainstream technology is in the third stage mainly focused on CSP and BGA, and is transitioning from traditional packaging (SOT, QFN, BGA, etc.) to advanced packaging (FC, FIWLP, FOWLP, TSV, SIP, etc.). Traditional packaging is mainly based on lead frame packaging, where chips are connected to the lead frame through soldered wires, and the pins of the lead frame are connected to the PCB, mainly including DIP, SOP, QFP, QFN and other packaging forms. The main functions of traditional packaging are chip protection, scale amplification, and electrical connection. Advanced packaging technology for packaging level reconstruction of chips can effectively improve the high functional density of the system. At present, advanced packaging mainly refers to flip soldering (Flip)
Chip, wafer level packaging (WLP), 2.5D packaging (Interposer), and 3D packaging (TSV), etc. The main difference between advanced packaging and traditional packaging lies in the difference between primary and secondary interconnection methods. The primary interconnection methods mainly include: traditional craftsmanship - Wire
Bonding (WB); Advanced Technology - Flip
Chip (FC). The secondary interconnection methods mainly include: traditional technology - through hole insertion type/surface mount; Advanced technology - Ball Grid Array (BGA)/Flat Grid Array LGA/Pin Grid Array (PGA). Therefore, FCBGA, FCLGA and other packaging are called advanced packaging. At the same time, traditional component packaging has evolved into system packaging, with packaging objects evolving from single chip to multi chip, and from planar packaging to three-dimensional packaging. Advanced Packaging - Taking TSMC as an Example. TSMC, as an industry leader, established a dedicated department for integrating wire and packaging technology as early as the end of 2008 to develop packaging technology. After more than ten years of technological research and development, it has accumulated multiple advanced packaging technologies and announced the launch of 3D Fabric in 2020 ™ Brand, further integrating the company's process technology and packaging technology. 3D
Fabric ™ This includes front-end system integration chip technology (SoIC), back-end on-chip packaging technology (CoWoS), and integrated fanout packaging technology (INFO). TSMC CoWoSCoWoS (Chip
On Wafer on Substrate is TSMC's first 2.5D advanced packaging technology launched in 2011, which includes three categories: CoWoS-S, CoWoS-R, and CoWoS-L. CoWoS-S consists of two parts: CoW and oS. The chips are connected to the silicon wafer through CoW technology, and then connected to the substrate through protrusions. This technology replaces traditional lead bonding with micro convex blocks and silicon perforation processes, stacking chips with different functions on the same silicon intermediate layer to achieve interconnection. It has the advantages of reducing package size, reducing power consumption, and improving system performance. Unlike CoWoS-S which uses silicon wafers as intermediate layers, CoWoS-R uses RDL as the intermediate layer to achieve interconnection between chips, greatly reducing production costs. CoWoS-L uses an interconnect with LSI (Local Silicon Interconnection) chips to interconnect chips, and achieves power and signal transmission through the RDL layer, making integration the most flexible. TSMC inFOInFO (Integrated)
Fan Out is a fanout wafer level system integration technology that includes InFO_ OS, InFO_ PoP and InFO_ LSI. TSMC's InFO technology uses polyamide instead of the silicon intermediate layer in CoWoS, reducing costs and packaging height, promoting large-scale production applications. InFO has high-density RDL, suitable for applications that require high-density interconnection and performance such as mobile and high-performance computing. TSMC SoIC In 2019, TSMC launched SoIC technology, including chip on wafer (COW) and wafer on wafer (WOW) solutions. Unlike CoWoS and InFO, the first two solutions stack logic chips, HBMs, interposers, etc. that have completed wafer level packaging during the packaging process, thus becoming the Back 3D manufacturing (Back
End 3D Fabric, while SoIC, in the front-end wafer manufacturing process, creates TSV vias on the logic chip and stacks them between the logic chips (or between the wafers of the logic chip). This process is called Front 3D Manufacturing
End 3D Fabric, after completing the wafer cutting after stacking, can be used for subsequent packaging similar to InFO and CoWoS. Therefore, SoIC and InFO/CoWoS are not in a parallel or substitutive relationship, but rather replace the single SoC used in InFO/CoWoS with multiple SoCs stacked in 3D. Compared to traditional packaging technologies, advanced semiconductor packaging has a higher number of I/Os, smaller size, and higher integration. The market size of advanced semiconductor packaging and integrated circuit packaging and testing has been increasing year by year. According to statistics from Yole and Jiwei Consulting, the global testing market size in 2022 was $81.5 billion, a year-on-year increase of 4.9%. It is expected that the market size will reach $96.1 billion by 2026, with a CAGR of 4.2% from 2022 to 2026. According to Frost&Sullivan's prediction, from 2021 to 2025, the scale of advanced packaging market in Chinese Mainland will increase from 39.9 billion yuan to 113.66 billion yuan, accounting for 32% from 15%, and the CAGR will be 29.91%, higher than the global average.
02 | Driving Factors Advanced Packaging Assists Moore's Law Continues Moore's Law, which states that when the price remains constant, the number of transistors that can be accommodated on an integrated circuit doubles every 18-24 months, meaning processor performance doubles approximately every two years, while the price drops by half. Since 2015, the development of advanced integrated circuit processes has slowed down, and the mass production progress of 7nm, 5nm, and 3nm processes has fallen behind expectations. With TSMC announcing a breakthrough in the 2nm process technology, the integrated circuit process technology has approached its physical size limit; At the same time, the cost of chip design has rapidly increased. Taking the design cost during the mainstream application period of advanced process nodes as an example, when the process node is 28nm, the design cost of a single chip is about 41 million US dollars, while when the process node is 7nm, the design cost has increased to 222 million US dollars. Advanced packaging helps Moore's Law continue. Advanced manufacturing processes are gradually approaching the physical limit, and more and more manufacturers are shifting their research and development direction from "how to make chips smaller" to "how to seal chips smaller". In the era of computing power, Chiplet has become a common choice. With ChatGPT bringing a new wave of AI applications, the demand for high computing power GPU chips in data centers is rapidly increasing. Compared to traditional consumer grade chips, computing power chips have a larger area, larger storage capacity, and higher requirements for interconnect speed. Chiplet technology can well meet the performance and cost requirements of these large-scale chips, and is therefore widely used. Chiplets, also known as small chips, are a type of die that satisfies specific functions. Through die to die interconnection technology, multiple module chips are packaged together with underlying basic chips to form a system chip. Unlike SoC, Chiplet decomposes different modules according to different calculations or functional units from the design stage, produces them into different dies, and uses advanced packaging technology to interconnect and package them. The manufacturing process of different modules can vary. Chiplet improves yield and reduces costs. Due to higher performance requirements, the die size of computing chips is usually much larger than that of past consumer grade products. For example, Nvdia's mainstream AI accelerator card products, die
The size usually exceeds 800mm2. In recent years, with the advancement of advanced processes, research and development production costs have continued to rise, and the yield of large-scale single SOC has been decreasing. Chiplet separates the different functional modules of a single SOC into independent small chips, greatly reducing the area of a single die, thereby improving yield and reducing costs. Chiplet imports HBM to solve the "storage wall" of HBM (High
Bandwidth Memory refers to high bandwidth memory, which vertically stacks multiple DRAMs using advanced packaging methods such as TSV silicon via technology. Against the backdrop of higher requirements for memory rate in high-performance computing applications, the use of advanced packaging technology in HBM effectively solves the memory rate bottleneck problem of traditional DRAM. The DRAM stack inside HBM belongs to 3D packaging, while the other parts of HBM and AI chips are sealed on the interposer and belong to 2.5D packaging. Chiplet drives chip computing power to break through. Currently, mainstream computing chip manufacturers on the market have all introduced Chiplet solutions, especially in the field of AI chips. Domestic AI chip manufacturers such as Bi Ren, Mu Xi, and Tian Tian have also launched heterogeneous integrated GPU products to import HBM storage. Semiconductor giants form the Chiplet Industry Alliance. On March 3, 2022, semiconductor giants such as AMD and Intel announced the joint establishment of the Chiplet Industry Alliance, with the goal of jointly creating Chiplet interconnect standards, promoting an open ecosystem, and developing standard specifications UCIE to establish high-speed interface standards for interconnectivity at the chip packaging level. The opportunity for domestic semiconductor manufacturers to break through advanced process restrictions is expected to be supported by Chiplet technology, which may help domestic semiconductor manufacturers break through overseas technology sanctions. In 2020, the United States included SMIC in the "physical list" and restricted the expansion of 14nm and below processes, resulting in domestic 14nm processes being unable to expand in the existing market. Chiplet technology can partially bypass overseas restrictions and surpass blockades downwards.
03 | Jintai Investment Suggestion 1) Sealing, testing, and manufacturing: Direct benefits, lack of investment opportunities in the primary market. The widely used 2.5D/3D packaging solution for computing chips is a significant upgrade to traditional packaging, but wafer manufacturers and packaging and testing manufacturers will still play an important role. But the current market pattern for manufacturing and packaging is relatively certain, and advanced packaging naturally requires high investment, with a huge advantage for leading companies. You can focus on the secondary market, as the primary market lacks investment opportunities. 2) Design side: Chiplet design ideas drive IP, EDA, and chip design. Chiplet technology can improve the flexibility and reusability of chip design, reduce manufacturing costs, and is expected to become one of the mainstream methods for future chip design. Chiplet cutting into small chips adds value to IP and is also beneficial for EDA companies. Chiplet may bypass advanced processes and benefit chip design companies. Representative enterprises include Saifang Technology, Xin Yaohui, Hexin Microelectronics, Xin Huazhang, Xin Ruiwei, Mu Xi, Bi Ren Technology, etc.
